All-In-One Scriptless Test Automation Solution!
Please ensure you read the below overview and requirements for this employment opportunity completely.
Location : Chandler, Arizona
Duration : up to 12 months contract with possible extension
Job Description
Pay Range : $60 – $68 / hr. The pay rate may differ depending on your skills, education, experience, and other qualifications.
Featured Benefits :
- Medical Insurance in compliance with the ACA.
- 401(k).
- Sick leave in compliance with applicable state, federal, and local laws.
This position is for either a Principal Engineer or Senior Principal Engineer Digital :
Basic Qualifications for Principal Engineer Digital :
B.S. degree in Electrical Engineering (Computer or Electrical), or related field with a minimum of 5 years of relevant professional work experience OR a M.S. degree with a minimum of 3 years of relevant professional work experience in EE / CE including experience in programmable logic design.Recent experience with Hardware Description Language (VHDL) and formal verification (OSVVM preferred) for FPGAs, CPLDs and / or ASICs.Ability to work in teams and communicate clearly across various levels of engineers.Ability to translate system performance and operational specifications into programmable logic requirements, design specifications, test specifications, and users’ guides.Preferred Qualifications :
Experience with Electronic Design Automation (EDA) Tools : Mentor Graphics ModelSim / QuestaSim, Radiant (Lattice), Vivado / ISE (Xilinx), Libero (Microsemi).Preferred candidate will have familiarity with :
Communication protocols (UART, SPI, I2C, 1-Wire, Ethernet, AXI, APB, SpaceWire).Static timing analysis and timing closure (setup and hold, slack, skew, etc.).Asynchronous clock domain crossing and general metastability mitigation techniques.Test-bench development, including timing-accurate bus functional models, complete functional coverage, etc.Working in an Agile project format, team-based environment, including Jira and Git environments.Formal verification with OSVVM.Basic Qualifications for Sr. Principal Engineer Digital :
B.S. degree in Electrical Engineering (Computer or Electrical), or related field with a minimum of 7 years of relevant professional work experience OR M.S. degree in EE / CE with 5 years of relevant professional work experience.Recent experience with Hardware Description Language (VHDL) and formal verification (OSVVM preferred) for FPGAs, CPLDs and / or ASICs.Ability to work in teams and communicate clearly across various levels of engineers.Ability to translate system performance and operational specifications into programmable logic requirements, design specifications, test specifications, and users’ guides.Preferred Qualifications :
A strong team player who also can work independently.Significant recent experience with VHISC Hardware Description Language (VHDL) and verification (OSVVM preferred) for FPGAs, CPLDs and / or ASICs.Preferred candidate will have familiarity with :
Communication protocols (UART, SPI, I2C, 1-Wire, Ethernet, AXI, APB, SpaceWire).Static timing analysis and timing closure (setup and hold, slack, skew, etc.).Asynchronous clock domain crossing and general metastability mitigation techniques.Test-bench development, including timing-accurate bus functional models, complete functional coverage, etc.Development in MATLAB / Simulink.High level programming languages (C / C ).Working in an Agile project format, team-based environment, including Jira and Git environments.J-18808-Ljbffr
Salary : $60 - $68
