What are the responsibilities and job description for the Sr ASIC/FPGA VHDL Design Engineer position at Switch4 LLC?
Title: Sr ASIC/FPGA VHDL Design Engineer
Location: Camden, NJ
Job Type: FTE/Permanent
Schedule: 9/80 Regular with every other Friday off
Job Description
Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed cryptography applications. S/he will architect and implement high-speed crypto architectures on ASICs/FPGAs, with hands-on design/debug with Ethernet, TCP/IP protocols. The company utilizes state-of-the-art EDA flows/methodologies, including Synopsys DC/Primetime/Synplify, Xilinx/Client/Microchip EDA with HLS, Mentor EDA Family suite: Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high-impact role in the organization to ensure robust quality and delivery of communication products.
Essential Functions
Location: Camden, NJ
Job Type: FTE/Permanent
Schedule: 9/80 Regular with every other Friday off
Job Description
Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed cryptography applications. S/he will architect and implement high-speed crypto architectures on ASICs/FPGAs, with hands-on design/debug with Ethernet, TCP/IP protocols. The company utilizes state-of-the-art EDA flows/methodologies, including Synopsys DC/Primetime/Synplify, Xilinx/Client/Microchip EDA with HLS, Mentor EDA Family suite: Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high-impact role in the organization to ensure robust quality and delivery of communication products.
Essential Functions
- Derive engineering specifications from system requirements and develop detailed architecture.
- Execute design (RTL and/or HLS (C to RTL)) and ensure RTL quality (RDC, CDC, Formal, Lint).
- Generate test plans.
- Perform module-level verification, synthesis/STA, Lab debug, SW-driven validation on Linux-based SOC evaluation boards.
- Participate in silicon/FPGA bring-up, characterization, and production ramp/support/collateral.
- BSEE required, MSEE preferred.
- 5 years of experience in developing, implementing, and verifying high-performance communications/networking ASIC/FPGA products.
- Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
- Proficiency with CDC, RDC, and Formal EDA.
- Proficient in VHDL is a must.
- Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado.
- Strong logic/board debug and analytical skills.
- Experience with project leadership and Earned Value Management (EVM).
- Excellent written, verbal, and presentation skills.
- Proficiency in C (OOP).
- Proficiency with FPGA design and writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
- Knowledge of PCIe, NVMe, USB protocols.
- Experience with High-Level Synthesis (Xilinx Vivado HLS, and/or Mentor Calypto).
- VHDL
