ASIC Digital Design Manager

Job Description and Requirements

Senior manager ASIC Digital Design - Sunnyvale

In order to make an application, simply read through the following job description and make sure to attach relevant documents.

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP Subsystems business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

We're looking for Senior ASIC Digital Design Manager to join Synopsys Solutions Group, Digital IP Subsystems Team in Sunnyvale, CA. Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs. Join the Synopsys Subsystems Team!

Requirements & Skills

• Experience in managing remote teams independently for a minimum of 5 to 10 years.
• As a Techno-Manager, knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR / PCIe / Ethernet / USB / UFS and other interface protocols.
• Programming skills such as System Verilog, TCL, Perl or Python.
• The ability to motivate the team and drive innovation.
• The ability to extract detailed requirements from high-level specifications.
• Good communication skills.
• Bachelor's or Master's degree in electronics with overall experience of 10 years.
• Techno managerial experience of 5 to 10 years.
• Hands-on / lead experience on Subsystems / SOC Design, Architecture, and Implementation.
• Experience with Verilog / System Verilog coding and simulation tools.
• Experience of implementation flows, namely : synthesis flow, lint, CDC, low power and others.
• Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components.

Responsibilities

Benefits

Inclusion and diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Company information : Smart, Secure Everything—From Silicon to Software. Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything—where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every day.

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Salary : $111,000 - $194,000