What are the responsibilities and job description for the RTL Design Engineer position at Synopsys Inc?
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a seasoned Logic Design Engineer with a passion for cutting-edge technology and a keen eye for detail. You thrive in a dynamic environment and are driven by the challenge of developing high-performance digital designs. With extensive experience in Serdes, or DDR/HBM, or Die to Die PHY logic, you excel at collaborating with cross-functional teams to deliver innovative solutions. Your expertise in PHY IP and SOC RTL design and verification, along with your ability to work independently with minimal oversight, makes you a valuable asset to any project. You possess a strong understanding of the full IP/SOC Design Cycle and have a proven track record of success in designing, developing, and evaluating physical IP such as SERDES, DDR and Die to Die Interconnect. Your excellent communication skills allow you to effectively convey complex technical concepts to both technical and non-technical audiences, and you are always eager to learn and adapt to new technologies and methodologies.
What You’ll Be Doing:
Designing and developing high-performance digital logic for the Synopsys' fast growing high-speed Die to Die interconnect IP portfolioCollaborating with cross-functional teams to define and implement best in class Die to Die IP design at PHY and controller levels.Design and optimize Die to Die IP for best in class performance, power, and area.Participating in the full Hard IP Design Cycle, including front-end and back-end design processes, post silicon support and customer supportConducting design reviews and providing technical guidance to junior engineers in highly matrixed global IP organizationStaying up-to-date with industry trends and emerging technologies to continuously improve design methodologies.
The Impact You Will Have:
Driving the development of world class high-performance D2D IPs to enable customer chiplet bases system design win across industries Contributing to the development of cutting-edge Die to Die technology that shapes the future of the semiconductor industry.Ensuring the successful delivery of high-quality, high-performance Die to Die IP for SOC/SIP.Enhancing the usability and adoption of Synopsys IP products through technical and engineering insights.Mentoring and guiding junior engineers to foster a culture of continuous learning and improvement in global matrixed organization Strengthening Synopsys' position as a leader in IP design, verification, and system integration.
What You’ll Need:
Extensive experience in Serdes, or DDR/HBM, or UCIe PHY architecture and logic impementation Expertise in design of Hard IP such as SERDES or DDR/HBM or Die to Die IO interconnectProficiency in SystemVerilog design and verification at SOC, IP and behavorial modeling at analog building block levelProficiency in end to end RTL to gate level design flow and methodology such as FEV, UPF, CDC, timing and ECO etcStrong understanding of the full IP/SOC Design Cycle.Excellent problem-solving skills and attention to detail.Experience in leading and driving technical solutions across organization The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
Who You Are:
A proactive and independent worker with minimal supervision.An effective communicator who can convey complex technical concepts.A collaborative team player who thrives in a cross-functional environment.A lifelong learner who stays up-to-date with industry trends and emerging technologies.A mentor and leader who guides and supports junior engineers.
The Team You’ll Be A Part Of:
You will join a highly skilled and collaborative team focused on developing high-performance digital designs for PHY, DDRIO, and UCIe PHY logic DE. Our team is dedicated to driving innovation and delivering cutting-edge solutions that shape the future of the semiconductor industry. We value teamwork, continuous learning, and a commitment to excellence, and we are excited to welcome a new member who shares our passion for technology and innovation.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a seasoned Logic Design Engineer with a passion for cutting-edge technology and a keen eye for detail. You thrive in a dynamic environment and are driven by the challenge of developing high-performance digital designs. With extensive experience in Serdes, or DDR/HBM, or Die to Die PHY logic, you excel at collaborating with cross-functional teams to deliver innovative solutions. Your expertise in PHY IP and SOC RTL design and verification, along with your ability to work independently with minimal oversight, makes you a valuable asset to any project. You possess a strong understanding of the full IP/SOC Design Cycle and have a proven track record of success in designing, developing, and evaluating physical IP such as SERDES, DDR and Die to Die Interconnect. Your excellent communication skills allow you to effectively convey complex technical concepts to both technical and non-technical audiences, and you are always eager to learn and adapt to new technologies and methodologies.
What You’ll Be Doing:
Designing and developing high-performance digital logic for the Synopsys' fast growing high-speed Die to Die interconnect IP portfolioCollaborating with cross-functional teams to define and implement best in class Die to Die IP design at PHY and controller levels.Design and optimize Die to Die IP for best in class performance, power, and area.Participating in the full Hard IP Design Cycle, including front-end and back-end design processes, post silicon support and customer supportConducting design reviews and providing technical guidance to junior engineers in highly matrixed global IP organizationStaying up-to-date with industry trends and emerging technologies to continuously improve design methodologies.
The Impact You Will Have:
Driving the development of world class high-performance D2D IPs to enable customer chiplet bases system design win across industries Contributing to the development of cutting-edge Die to Die technology that shapes the future of the semiconductor industry.Ensuring the successful delivery of high-quality, high-performance Die to Die IP for SOC/SIP.Enhancing the usability and adoption of Synopsys IP products through technical and engineering insights.Mentoring and guiding junior engineers to foster a culture of continuous learning and improvement in global matrixed organization Strengthening Synopsys' position as a leader in IP design, verification, and system integration.
What You’ll Need:
Extensive experience in Serdes, or DDR/HBM, or UCIe PHY architecture and logic impementation Expertise in design of Hard IP such as SERDES or DDR/HBM or Die to Die IO interconnectProficiency in SystemVerilog design and verification at SOC, IP and behavorial modeling at analog building block levelProficiency in end to end RTL to gate level design flow and methodology such as FEV, UPF, CDC, timing and ECO etcStrong understanding of the full IP/SOC Design Cycle.Excellent problem-solving skills and attention to detail.Experience in leading and driving technical solutions across organization The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
Who You Are:
A proactive and independent worker with minimal supervision.An effective communicator who can convey complex technical concepts.A collaborative team player who thrives in a cross-functional environment.A lifelong learner who stays up-to-date with industry trends and emerging technologies.A mentor and leader who guides and supports junior engineers.
The Team You’ll Be A Part Of:
You will join a highly skilled and collaborative team focused on developing high-performance digital designs for PHY, DDRIO, and UCIe PHY logic DE. Our team is dedicated to driving innovation and delivering cutting-edge solutions that shape the future of the semiconductor industry. We value teamwork, continuous learning, and a commitment to excellence, and we are excited to welcome a new member who shares our passion for technology and innovation.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
