Senior Staff Engineer, CAD - Packaging Group

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced engineer with a deep understanding of System-on-Chip (SoC) and IP architecture. With a background in CAD engineering and signal integrity, you are passionate about developing and implementing advanced methodologies and technologies. You thrive in collaborative environments, working closely with technical leaders and customers to deliver innovative solutions. You have a strong foundation in ASIC implementation techniques and chip assembly methodologies, and you excel in technical leadership roles. Your expertise in signal integrity fundamentals, packaging designs, and scripting in Unix/Linux environments sets you apart. You are dedicated to continuous learning and staying abreast of new technologies and tools in the semiconductor industry.

What You'll Be Doing:

• Developing and implementing SoC/IP flows and methodologies for signal and power integrity and advanced packaging architecture.
• Utilizing Ansys Multi-Physics tools and scripting design flows around tools like HFSS, SiWave, Redhawk for EM-IR (both static and dynamic), and Redhawk for thermal analysis.
• Conducting PDN analysis and generating CPM models, performing chip-package-PCB system simulations in both time and frequency domains.
• Preparing design flows and methodologies with a strong understanding of PCB, packaging, and RDL designs.
• Collaborating with other Synopsys teams, including BU AEs and sales, to develop and deploy packaging and signal integrity solutions.
• Ramping up on new 3DIC packaging and SI tools and methodologies using Synopsys products to enable customers.

The Impact You Will Have:

• Enhancing the reliability and performance of SoC designs through advanced packaging and signal integrity solutions.
• Driving innovation in semiconductor technology by developing cutting-edge methodologies and flows.
• Contributing to the success of customer projects by providing expert technical guidance and support.
• Improving the efficiency and effectiveness of chip design processes with automated tools and techniques.
• Enabling customers to achieve their most challenging design goals with comprehensive and integrated solutions.
• Advancing the state-of-the-art in semiconductor packaging and signal integrity through continuous learning and adaptation.

What You'll Need:

• Bachelor's, Master's, or PhD in Electrical Engineering with 8 years of experience in ASIC implementation techniques and chip assembly methodologies.
• Strong knowledge of signal integrity fundamentals, including PDN, EMIR, basic analog circuits, T-line theory, crosstalk, S-parameters, and channel simulations.
• Experience with 2.5/3D packaging and knowledge of CoWoS, InFo, and RDL is a plus.
• Excellent technical documentation skills.
• Proficiency in Unix/Linux environments and the ability to run EDA tools through scripting languages.
• Demonstrated ability to devise innovative design solutions and lead technical projects.

Who You Are:

You are a collaborative and innovative engineer with a passion for technology and a commitment to excellence. You possess strong analytical and problem-solving skills, and you are adept at communicating complex technical concepts to diverse audiences. You are a lifelong learner, always seeking to expand your knowledge and expertise. Your ability to work effectively in cross-functional teams and your dedication to customer success make you a valuable asset to any project.

The Team You'll Be A Part Of:

You will be part of the System Solutions Group (SSG) at Synopsys, a team of experts in various Synopsys technologies. The team is dedicated to delivering architecture, design, verification, implementation, tools, and methodologies to enable customers to complete their most challenging SoC design projects. The team's work spans from sub-blocks to full turnkey end-to-end SoCs, and it serves a diverse range of customers, from start-ups to industry leaders, commercial companies, and government agencies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.