Physical Design Engineer (Sunnyvale, CA)

Responsibilities

• Responsible for implementation of ultra-high performance and low power data processing chip
• Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs
• Floor-planning, experimenting with placement and routing techniques for better PPA
• Do timing closure for very high frequency designs with possible hand placement of logic when needed
• Help define low latency / low skew clock tree methodology / design
• Help define appropriate power grid structures to meet EM / IR goals
• Scripting and automating flows to improve turn-around times

Qualifications

J-18808-Ljbffr