Demo

Emulation Engineer

Talently
Cupertino, CA Full Time
POSTED ON 3/8/2025
AVAILABLE BEFORE 4/6/2025

Job Title: Emulation Software Engineer

Location: Cupertino, CA

Salary: 200-300K

Skills: Palladium, Protium, Veloce, Zebu, C/C , System Verilog, Verilog, UVM, DFT, Verdi, Slimform


About Company / Opportunity:

We are building AI chips that are hard-coded for individual model architectures. Our first product only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With our ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.


Responsibilities:

  • Oversee SoC bring-up on emulation platforms; diagnose and resolve failing SoC/Processor tests.
  • Develop innovative techniques to accelerate pre-silicon validation and software development.
  • Provide support for various emulation environments, utilizing advanced emulation techniques including C/C DPI transactors, coverage analysis, and in-circuit emulation for high-speed protocols.
  • Collaborate closely with teams across Design, DV, Silicon Validation, Performance, and Software, and partner with leading emulation vendors to enhance platform capabilities and troubleshoot complex issues.
  • Develop high-performance software to capture debugging signals and create associated tooling to surface valuable insights for users.
  • Implement a hybrid emulation environment using custom DPI-based streaming transactors.
  • Create highly configurable chip-to-chip network models using emulation-efficient primitives.


Must-Have Skills:


  • Hands-on experience with emulation on platforms such as Palladium, Protium, Veloce, or Zebu, covering design bring-up, build flows, debugging, and performance tuning.
  • Strong experience with C/C and Linux system development. Proficiency with SystemVerilog and Verilog, including DPI-based interfaces.
  • Practical experience with scripting languages (i.e., Python) for automation.
  • Experience working with UVM verification environments.
  • Background in design verification, DFT, and testbench modeling.
  • Familiarity with waveform debug tools such as Verdi or SimVision.


Benefits

  • Highly competitive comp packages with amazing stock incentives!
  • Full medical, dental, and vision packages, with 100% of premium covered
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino

Salary : $200,000 - $300,000

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