What are the responsibilities and job description for the PCIE Engineer position at Tanisha Systems, Inc?
Role: Senior PCIE Engineer
Location: Santa Clara, CA (Onsite)
Hiring Type: Contract or Full Time Both are fine
Mode : Depends on the project delivery. During peak time can be 5 days, non-peak time can be 1-2 days.
Key Responsibilities:
- Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
- Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
- Develop and execute comprehensive verification plans, including testbenches and test cases.
- Collaborate with design, architecture, and software teams to define and implement verification strategies.
- Utilize advanced verification methodologies, including UVM.
- Mentor and guide junior engineers, fostering a collaborative and innovative team environment.
Preferred Experience:
- 10 years of senior Pre-silicon verification engineer with PCIE physical, link layer experience in typical networking application products.
- Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
- Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
- Require familiarity with verification management tools.
- Prior years of experience in pre-silicon validation within the semiconductor industry
- Demonstrated ability to grasp new technical concepts quickly
- Experience with IP/System level bring-up, SOC debug techniques and methodologies
- Strong analytical/problem solving skills and pronounced attention to details
- Excellent written and verbal communication skills
- Self-starter, strong collaborator, and able to independently drive tasks to completion
- Strong organizational skills and ability to handle multiple issues at the same time
