Staff/Sr. Staff PHY Design Engineer

If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work not just singing the same song every day, you’ll find your playground at Innophase IoT.We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!Job Description : Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT / BLE micro-architecture and design. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm and verification engineers.Your specific responsibilities may include but are not limited to the following : Develop and refine Digital Signal Processing engines for wireless communication systems.Develop micro-architecture, and SystemVerilog RTL to meet size, timing, and power target.Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and optimizations.Develop, and refine design, verification and analysis tools and flows, as needed.Work closely with Verification, and Validation teams on test-plans, coverage-analysis.Work closely with Physical Design teams to provide guidance on Floor planning, specification of constraints, and timing closure.Required Qualifications : BSEE or MSEE, with experience in ASIC development and / or FPGA prototyping.7 years of experience in RTL design using Verilog, SystemVerilog.Understanding of Digital Signal Processing theory, and mapping to design.Experience in WiFi Physical Layer, and / or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and / or other Physical layer (Ethernet) technologies.Ability to work independently, and proactively identify and resolve issues.Experience with Incisive / Excellium / VCS, Verdi, Jasper / Spyglass or equivalent tools.Experience in partitioning, synthesis, placement, timing closure for FPGA and / or ASICs.Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.Enjoy debugging, and problem solving in a team environment.Preferred Qualifications : Experience in Low Power design development, involving multiple power, and voltage domains.Embedded SW & HW design is a strong plus.Experience with Python, Perl, Tcl, C / C and shell scripts.Experience with lab debug, multi-team, multi-site working environment is a strong plus.Experience with ASIC and FPGA synthesis flows utilizing industry leading flows.Experience using PowerArtist / Joules and providing actionable feedback into design.We bring together the best in technology, drive innovation to create the best ULP wireless IoT solutions and user experiences in home, building and industrial automation and wearables. We create career opportunities across a wide range of locations, disciplines and are at the forefront of change, thanks to our remarkable people, who bring cutting-edge products and solutions to our customers. If you share in our passion for teamwork, our vision to revolutionize the IoT industry and our goal to lead the future in technology, we want you to fast-forward your career at InnoPhase IoT.It is key to unleash the potential in every employee, every team, every leader, and the company herself. We know employees perform best when motivated, appreciated and recognized, and can be themselves. We are committed to building a culture where every voice can be heard, everyone has room for growth and can make meaningful contributions. At the end of the day, we want success not just for the company, but also for everyone who believes in the company, the vision, and the future.Apply for this job#J-18808-Ljbffr