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Physical Design Engineer

Technical-Link N. America
San Jose, CA Full Time
POSTED ON 1/17/2025
AVAILABLE BEFORE 4/15/2025

Physical Design / Place and Route Engineer

Responsibilities

  • Cadence - Innovus PNR flow expertise.
  • Experience with importing design in the Virtuoso environment.
  • Experience with physical design verification using stand alone Caliber.
  • Experience with putting a chiptop for a TO.
  • Experience with bump map creation.
  • Familiar with LEF / DEF generation for chip level as well as block level.
  • Familiar with TSMC 7nm or below nodes.

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