Principal Design Verification Engineer

We are seeking a Principal Design Verification Engineer for an American multinational IT company!

Pay $100/HR to $140/HR

This position can be Remote within the continental US.

We are looking for a Principal Design Verification Engineer to lead the verification of high-performance, packet-based data transfer protocols in cutting-edge semiconductor designs. This role focuses on ensuring the integrity, reliability, and performance of networking and interconnect solutions used in high-speed computing, AI accelerators, and data centers.

Key Responsibilities:

• Verify high-speed protocols (Ethernet, Infiniband, PCIe) for compliance and performance.
• Configure & validate high-speed SERDES and die-to-die interconnects for chiplet-based architectures.
• Verify ARM processor subsystems, ensuring integration and cache coherence.
• Validate JTAG/SBUS functionality and implement error injection tests.
• Develop SystemVerilog/UVM testbenches and conduct coverage-driven verification.

Qualifications:

• 15 years in ASIC/SoC Design Verification.
• Expertise in high-speed data transfer protocols, SERDES, and chiplet interconnects.
• Hands-on experience with ARM subsystems, JTAG/SBUS, and error injection.
• Proficiency in SystemVerilog/UVM, Python, or Perl.
• Experience with industry-standard simulation tools (VCS, Questa, Xcelium).

Preferred:

• Formal verification, FPGA prototyping, and AI/HPC chip experience.
• Strong debugging skills (Verdi, SimVision, DVE).

Join us to work on next-generation semiconductor designs in a fast-paced, innovative environment!

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