What are the responsibilities and job description for the Design Engineer-Full Chip leve-Minimum 8 years Required position at Timely Find?

We are hiring for our client - Mega Cloud Lab.

Role : Design Engineer

Location : Santa Clara, CA (Onsite)

Longterm Contract

8-10 years of design experience in developing synthesis constraint at module and Full Chip level

Experience in promoting subsystem level RDC/CDC constraint to SoC Top
Experience in debugging and triaging Lint CDC/RDC errors or issues
Experience in converting spyglass constraints to realintent constraints
Experience in creating lint RDC/CDC constraints both at IP level , Fullchip or Top level
Experience in promoting IP level or SoC Constraints

8-10 years of design experience in developing synthesis constraint at module and Full Chip level

Experience in promoting subsystem level RDC/CDC constraint to SoC Top
Experience in debugging and triaging Lint CDC/RDC errors or issues
Experience in converting spyglass constraints to realintent constraints
Experience in creating lint RDC/CDC constraints both at IP level , Fullchip or Top level
Experience in promoting IP level or SoC Constraints

Skills: creating lint rdc/cdc constraints,promoting ip level or soc constraints,subsystem level rdc/cdc constraint promotion,triaging lint cdc/rdc issues,cdc,design experience,soc,lint,synthesis constraint development,rdc/cdc constraint promotion,rdc,debugging and triaging lint cdc/rdc errors,debugging lint cdc/rdc errors,synthesis,design,converting spyglass constraints to realintent constraints

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Design Engineer-Full Chip leve-Minimum 8 years Required

What are the responsibilities and job description for the Design Engineer-Full Chip leve-Minimum 8 years Required position at Timely Find?

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Job openings at Timely Find

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