What are the responsibilities and job description for the ASIC Engineer position at TPI Global Solutions?
We are seeking a Senior ASIC Engineer with a focus on Static Timing Analysis to join our team. This position requires a strong background in ASIC design, timing analysis, and debugging to ensure the quality and performance of complex digital designs. The role will involve executing custom regression scripts, performing quality checks, and addressing any timing violations to meet design milestones.
Key Responsibilities:
- Timing Analysis: Perform static timing analysis on multimode, multimillion gate designs with multiple partitions.
- Regression and Quality Checks: Execute custom regression scripts to check for design integrity and quality.
- Report Review: Review and analyze PT/DC checks and timing reports to identify and resolve issues related to design and constraints.
- Debugging: Address basic issues such as SDC loading errors, clock constraints, and QoR violations.
- Progress Tracking: Summarize regression results periodically to track progress and ensure deadlines are met.
- Collaboration: Work closely with cross-functional teams to ensure accurate timing closure and high-quality deliverables.
Required Qualifications:
- Experience: Minimum of 6-8 years of experience in ASIC design and timing analysis.
- Tools: Familiarity with EDA tools such as Synopsys Design Compiler/Primetime, Spyglass, and Fishtail (or similar tools).
- Skills: Strong attention to detail, excellent communication (both written and verbal), and a fast learner capable of multitasking and adapting quickly to new tools/flows.
- Education: A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required.
Preferred Experience:
- Experience with multimode, and multimillion gate designs and handling complex designs with multiple partitions.
- Strong debugging skills for resolving timing and constraint-related issues.
- Ability to manage and prioritize multiple tasks in a fast-paced environment.
