ASIC/RTL Design Engineer

Job Description:

We are seeking a highly skilled and experienced ASIC/RTL Design Engineer - Senior to join our team at AMD in Santa Clara, CA. The successful candidate will work on cutting-edge System-on-Chip (SoC) designs in advanced digital CMOS processes, contributing to the development of next-generation hardware for a variety of applications, including ARM cores, Ethernet, DDR, DMA, PCIe, SATA, and AMD's internal IPs.

As a Senior RTL Design Engineer, you will play a key role in designing, verifying, and delivering high-performance, custom SoCs. You will work closely with cross-functional teams to ensure the successful execution of SoC designs from architecture to silicon bring-up.

Key Responsibilities:

• RTL Design: Develop and write Register Transfer Level (RTL) code for the design of digital circuits. Convert micro-architectural specifications into functional logic.
• SoC Architecture and Integration: Contribute to the definition and architecture of System-on-Chip (SoC), and integrate ARM cores and other IP cores (Ethernet, DDR, DMA, PCIe, SATA, etc.).
• Verification & Debugging: Perform verification, emulation, and debugging of designs to ensure compliance with specifications. Troubleshoot and resolve design issues.
• Synthesis & Timing Closure: Contribute to synthesis processes and ensure timing closure through tools like PrimeTime.
• Quality Assurance: Run front-end checks including Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC). Debug and resolve issues to maintain high design quality.
• Collaboration: Work closely with physical execution, software, and silicon bring-up teams to ensure seamless integration of designs.
• Documentation & Communication: Maintain thorough documentation of design processes and communicate effectively with internal teams to ensure alignment across design phases.

Required Skills & Experience:

• SoC Design: Solid experience with System-on-Chip (SoC) design, including RTL coding, IP integration, verification, and debugging.
• Tool Expertise: Strong working knowledge of tools used in the ASIC design flow, including synthesis, linting, CDC, RDC, and PrimeTime.
• Programming: Proficiency in RTL coding (Verilog/VHDL), TCL scripting, and Python for automation and design tasks.
• ARM Cores & IPs: Hands-on experience with ARM cores and standard I/O interfaces (Ethernet, DDR, PCIe, SATA, etc.).
• Experience: Around 10 years of experience in ASIC design, or less with significant hands-on experience.
• Education: A Bachelor’s degree in Electrical Engineering or Computer Engineering (preferred).
• Problem-Solving & Debugging: Experience in debugging complex designs and resolving timing, logic, and verification issues.

Desired Attributes:

• Technical Leadership: Ability to guide junior engineers, review designs, and contribute to team decision-making.
• Strong Communication: Excellent verbal and written communication skills for effective collaboration with cross-functional teams.
• Organizational Skills: Ability to manage multiple tasks efficiently and work in a fast-paced, dynamic environment.
• Initiative and Discipline: Proactive approach to problem-solving and strong follow-through on tasks.