FPGA Design/Verification Engineer

Job Description

Job Description

Title : FPGA Design / Verification Engineer

Rate : $80.00 / hr - $110.00 / hr on W2

Location : Sunnyvale-CA "OR" Denver-CO (Onsite)

Job ID : 17040-1

Shift : 4 / 10-1st Shift

Duration : 12 months contract to hire position.

US Citizenship required.

Note : You will need to be available to be in office at least 1 day a week - more depending on program need therefore the candidates must be local to either Sunnyvale, CA or Denver, CO

Job Description :

Seeking a well-rounded Release Engineer who excels in release process; Contract Deliverable Requirements List (CDRL), Subcontract Deliverable Requirements List (SDRL), Statement of Work (SOW), release cycles, schedule, document management and tracking as well as data collection, infrastructure and analysis. The ideal candidate will have experience or be familiar with front-end ASIC or FPGA processes, tools, development lifecycle and risks.

YOU WILL :

Collaborate with Technical Leaders in the development and review of CDRL items

Reviewing the contract Statement of Work and evaluating all required CDRLs are relevant to FPGA

Reviewing the applicable CDRLs to determining the frequency of release, and creating a schedule for CDRL deliveries to ensure that they are tracking to on-time release

Working closely with Data Management (DM) to ensure that our schedules for upcoming CDRL releases are synchronized, and that CDRLs are released on time, adjudicated by the customer and by key stakeholder comments

Work with FPGA Technical Leads to ensure awareness of upcoming CDRL releases and tracking of the same

Ensure that the CDRL documents match the required Data Item Description (DID) requirements for content and format

Work with the Integrated Product Team (IPT) schedule to ensure that the CDRLs are also correct in the Integrated Master Schedule (IMS)

Report CDRL metrics and upcoming CDRL deliverables at the weekly Leader meetings

Place the FPGA documents into document management and track the approvals to ensure that they are done in a timely manner

For FPGA releases, ensure that the CDRL contents are met with the FPGA release, that the Circuitware is delivered to the customer on time, and that all CDRL coordination is done with DM

Prepare CDRL and file release metrics and projections for analysis by Technical Leads and Management

Assist with proposal creation, leveraging data from past projects

Set up development and release tracking infrastructure for the development team to ensure consistency and completeness

Communicate well with ASIC / FPGA engineers, Technical Leads and Managers, understanding the vernacular and lifecycle of semiconductor development.

YOU WILL TYPICALLY HAVE :

5 years of professional experience.

Willing and able to obtain and maintain a DoD Secret clearance, thus you are a US Citizen.

Basic Qualifications :

Bachelor of Science or higher from an accredited college in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience / combined education.

2 years of professional engineering experience

1 year of experience in design, debug and / or verification of ASICs or FPGAs

Understand industry standard versioning schemes (e.g. Semantic Versioning)

Understand source control (e.g. Git, Subversion) and build management (e.g. GitLab Releases, Nexus, Artifactory)

Linux

Desired skills :

Demonstrated self-starter and voracious learner with high Social skills

Microsoft Office

Microsoft Project

Atlassian Jira

Ability to obtain a TS / SCI clearance

Python, SQL

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Salary : $80 - $110