Silicon DDR Bringup and Validation Engineer

JOB TITLE: Silicon DDR Bringup and Validation Engineer
**TOP 3 SKILLS:**

• In-depth knowledge of system architecture, performance/power, and software of DDR subsystems for server applications.
• Experienced level knowledge of C/C and Python.
• Relevant knowledge of verification methodologies, Verilog simulation, waveform viewers, and emulation.

LOCATION: Santa Clara CA , Austin TX, Portland OR, Fort Collins CO
DURATION: Direct
RATE RANGE: $140,000 - $160,000

SUMMARY:

The role of the Silicon DDR Bring-up and Validation Engineer involves the initiation and validation of the DDR subsystems within Rivos SOC design. This position demands a comprehensive grasp of cutting-edge DDR design tailored for server applications, covering aspects such as physical design, logic, performance, system, and software. Responsibilities include test generation, configuring test infrastructure, planning and executing bring-up processes, and developing and executing validation plans specifically for DDR systems. Currently, the intention is to fill technical lead or senior technical staff positions for this role.

RESPONSIBILITIES:

• As a lead, you will lead an engineering team responsible for designing, implementing and executing DDR subsystem silicon bring-up plans, including functional and performance tests, to validate the subsystem for the silicon product to meet the product requirements.
• Collaborate with cross-functional teams including design, architecture, firmware, and software to ensure successful subsystem bring-up and validation.
• Work with vendors and partners to ensure successful subsystem bring-up and validation, including reviewing and providing feedback on vendor documentation, and coordinating with vendor support teams.
• Debug and root-cause issues found during subsystem bring-up and validation, and work with cross-functional teams to implement corrective actions.
• Design and execute sensitivity experiments to fine-tune and optimize DDR subsystems for enhanced performance and power efficiency.
• Drive continuous improvement of subsystem bring-up and validation processes and methodologies, including automation, tool development, and documentation.
• Maintain up-to-date knowledge of the subsystem technology and industry trends.

QUALIFICATIONS:

• In-depth knowledge of system architecture, performance/power, and software of DDR subsystems for server applications.
• Experienced level knowledge of C/C and Python.
• Relevant knowledge of verification methodologies, Verilog simulation, waveform viewers, and emulation.
• Experience in silicon debug for logic, software, and physical issues.
• Experience with lab instruments such as logic analyzers and oscilloscopes.
• Strong ability to triage issues and develop environment and tools.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.

• PhD, Master's Degree or Bachelor's Degree with more than 5 years of experience in DDR technical subject area.

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