Design Verification Engineer

Job Title : Design Verification Engineer
Location: Bay Area, CA or Austin, TX ( Onsite )
Duration/Term: Long Term Contract

Job Description:

The ASIC Design Verification Engineer will be responsible for constructing scalable, configurable, and reusable DV/Performance verification environments. The role involves writing System Verilog and/or System C models, developing UVM testbenches, creating validation vectors, and ensuring functional completeness for IP, Subsystem, or SoC level designs.

Key Responsibilities:

• DV/Performance Verification Environment: Design and construct highly scalable, configurable, and reusable verification environments for ASIC/IP/Subsystem/SOC.
• System Verilog/System C Models: Write System Verilog and/or System C models for simulation, ensuring accuracy and alignment with project requirements.
• UVM Testbenches: Develop UVM models, checkers, stimulus, and register models using constrained random methodologies for comprehensive verification.
• Test Plan & Validation: Compose test plans and validation vectors to ensure the functional completeness and coverage of the design.
• Design for Verification: Apply assertion-based design strategies, code coverage, functional coverage, and back-annotation techniques.
• High-Level Verification Flows: Work with high-level verification flows such as SV, UVM, or C , utilizing industry-standard verification tools.
• Problem Solving: Demonstrate strong problem-solving skills to address complex verification challenges.
• Communication: Provide clear communication (both written and oral) on verification progress, challenges, and results.

Qualifications:

• Experience Requirements:
• Rich experience in ASIC design/verification, particularly in IP, Subsystem, or SoC levels.
• Proven experience in writing System Verilog and/or System C models for simulation.
• Hands-on experience with UVM models, checkers, and stimulus development.
• Experience with design-for-verification strategies, including assertion-based design and code/functional coverage.
• Technical Expertise:
• Expertise in using UVM testbenches and constrained random methodologies for simulation.
• Strong knowledge of high-level verification flows such as SV, UVM, or C , and industry-standard verification tools.
• Communication Skills: Excellent written and verbal communication skills for presenting verification results and collaborating with the team.
• Problem Solving: Strong analytical and problem-solving skills to troubleshoot and resolve verification issues.

Key Skills: System Verilog, System C, UVM, assertion-based design, code coverage, functional coverage, test plans, gate-level simulation, back-annotation, SV/UVM/C verification flows.

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