What are the responsibilities and job description for the Senior Design Verification Engineer position at Wipro?
Design Verification Engineering Services
Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests
Integration / development of C tests / Application Programming Interface (“APIs”) and software build flow
Integration of UVM testbenches
Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements
Continuous integration and / or regression testing setup and debug for simulation at both RTL and Gate Level Netlist
Unified Power Format (“UPF”) power aware simulation / emulation
XProp simulation / regression TestBench creation and maintenance
Coverage collection and closure
Documentation of tests, testbench, use-cases, exclusions, and status
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Atlanta, GA
Full Time