What are the responsibilities and job description for the ASIC RTL/SoC Design Engineer position at Yochana?
Role : ASIC RTL / SoC Design Engineer
Location : Fremont, CA (Onsite)
Duration : Full Time
Responsibilities :
- Lead RTL design, simulation, and verification efforts for Client ASIC / SoC products, ensuring robust and efficient designs
- Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
- Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
- Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
- Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and / or in-memory computing applications
- Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
- Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
- Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
- Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
- Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery
Requirements :
