What are the responsibilities and job description for the Design for Test Engineer (DFT) position at Yoh - A Day & Zimmerman Company?
Job Details
Design for Test Engineer (DFT)
The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions.
Scope:
Implementation of DFT features into RTL (using Verilog).
Understand DFT Architectures & micro-architectures.
ATPG & test coverage analysis using industry standard tools.
JTAG/Scan Compression, & ASST implementation.
Gate level simulation (using Synopsys VCS & Verdi).
Support silicon bring-up/debug.
MBIST planning, implementation, & verification.
Support Test Engineering on planning, patterns, & debug.
Develop efficient DFx flows & methodology compatible with front end and physical design flows
Required:
Degree with 5 years of experience in advanced DFx techniques.
Experience with DFx, implementing in finFET technologies.
ATPG & DFx insertion CAD tools.
Understanding of SystemVerilog & UVM.
Solid RTL coding for DFx logic including lock-up latches, clock gates, & scan anchors.
Understands low-power design flows such as power gating, multi-Vt & voltage scaling.
Understands high-performance, low-power design fundamentals.
Understands fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, & Cell Aware.
Exposure to post-silicon testing & tester pattern debug are major assets.
Pluses:
Experience with Fault Campaigns.
Estimated Min Rate: $40.00
Estimated Max Rate: $80.00
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions.
Scope:
Implementation of DFT features into RTL (using Verilog).
Understand DFT Architectures & micro-architectures.
ATPG & test coverage analysis using industry standard tools.
JTAG/Scan Compression, & ASST implementation.
Gate level simulation (using Synopsys VCS & Verdi).
Support silicon bring-up/debug.
MBIST planning, implementation, & verification.
Support Test Engineering on planning, patterns, & debug.
Develop efficient DFx flows & methodology compatible with front end and physical design flows
Required:
Degree with 5 years of experience in advanced DFx techniques.
Experience with DFx, implementing in finFET technologies.
ATPG & DFx insertion CAD tools.
Understanding of SystemVerilog & UVM.
Solid RTL coding for DFx logic including lock-up latches, clock gates, & scan anchors.
Understands low-power design flows such as power gating, multi-Vt & voltage scaling.
Understands high-performance, low-power design fundamentals.
Understands fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, & Cell Aware.
Exposure to post-silicon testing & tester pattern debug are major assets.
Pluses:
Experience with Fault Campaigns.
Estimated Min Rate: $40.00
Estimated Max Rate: $80.00
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit to contact us if you are an individual with a disability and require accommodation in the application process.
For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Salary : $40 - $80
