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ISP RTL Design Engineer

POSTED ON 4/20/2025 AVAILABLE BEFORE 5/13/2025
OMNIVISION Singapore 609935, Full Time
Responsibilities
  • Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
  • Verify Logic at ISP level and Digital System level
  • Optimize Design for less gate count and low power consumption
  • Drive ISP Design activities in close collaboration with ISP Algorithm Team
Requirements
  • Minimum MSEE, or BSEE, or related/equivalent discipline
  • Experience / knowledge in RTL, C/C programming and verification
  • Strong debugging and problem-solving skills
  • Good communication and interpersonal skills
  • Result oriented and embrace change behaviours
  • C /SystemC knowledge with High Level Synthesis experience is a plus.
  • Experience / knowledge in CMOS Image Sensor is a plus

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