IPU/AI Logic Design Lead

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THE ROLE:

We are seeking a capable and motivated design lead to be part of front-end design team of next generation IPU/AI Silicon. You will take part in design and implementation of high-performance, low-power IP for AI/ML applications.

This role will require deep understanding of design implementation and flows, tools and methodologies , including power intent UPF specifications. This role requires 10 years of experience in logic design & 5 years of experience leading teams & driving project.

THE PERSON:

Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as individual contributor and as a lead and has a history of achieving quality deliverables meeting schedule in fast pace, Innovation & stakeholder interaction. Basic knowledge of ML, power-performance-Area optimizations, low power designs preferred.

KEY RESPONISIBILITES:

• Logic design of IPU / AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirement
• Drive the design execution, mentoring team of engineers & being responsible for overall execution Quality & schedule. 
• Ensure Design meets performance, power and Area targets & good verification coverage for zero bugs in silicon.
• RTL design and debug of relevant blocks to realize the low power architecture in silicon. 
• Work with verification and physical design teams to achieve high quality design and successful tape out
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas.
• Perform RTL-Level design verification and debugging as needed
• Stay current with industry trends and technologies related to digital circuit design

PREFERRED EXPERIENCES:

• 15 years of Strong design expertise in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex IP like CPU/GPU etc..
• Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
• Expertise in Low power digital design and analysis. Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
• Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
• Good Understanding of Machine learning concepts.
• hands-on with TCL, Perl, Python scripting, 
• Strong verbal and written communication skills
• Ability to organize and present complex technical information

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-RF1 

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.