Logic Design and Timing Lead

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THE ROLE:

We are seeking a seasoned Logic Design Expert with significant experience in RTL and Timing and with a background in DFx.

You have had significant success driving Design Methodologies, RTL, Timing and Architecture to tapeout and production. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design, verification, validation, CAD and product engineering teams.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Architecture, microarchitecture, RTL for a comprehensive test, debug, yield and characterization IP
• IP collateral deployed across the business unit involving 20 IP teams.
• Define and own timing constraints to be applied by users of IP
• Define and own complete quality checking and constraints for lint, cdc, rdc, lec and other front end design requirements
• Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
• Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets and Performance/Power Verification sign offs
• Engage with validation and product teams on test plan, coverage, silicon bringup and silicon debug issues
• Contribute to front-end, DFx and timing methodologies
• Drive innovation in a rapidly changing technology environment

 PREFERRED EXPERIENCE:

• Solid foundation in logic design, switching theory and timing
• Solid foundation in design technology and design methodology
• Demonstrated expertise with design tools and design flows
• Excellent communication, management, and presentation skills.
• Experience with supporting silicon debug and diagnosis
• Skilled at collaborating with multi-disciplinary teams across different geographies
• Desirable experience:
• Experienced in driving technical specifications for SoC and IP level architecture, IP and methodologies
• Expertise in one or more of the following: Clocks, Resets, Harvesting, Yield, Scan, ATPG, MBIST, Repair, Yield, Power Management

 ACADEMIC CREDENTIALS:

• Education: Bachelor’s, Master’s or PhD degree in electrical engineering, computer engineering or related discipline

LOCATION:  San Jose, CA 

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.