What are the responsibilities and job description for the Design Verification Engineer position at Advantra Consulting Group?
Job Details
Hello,
This is Syed from Advantra. We have an immediate requirement for a Design Verification Engineer with a client in Mountainview, CA. This is a contract-position. If you are interested or know someone who would be a good fit, please share your updated Resume at or call me at .
Job Title: Design Verification Engineer
Location: Mountain View, CA (Working from Google office)
Type: Long term Contract
Responsibilities:
- Strong understanding of SV and UVM and good debugging skills.
- Understanding of AMBA protocols.
- Understand design specs and develop test plans based on functional and architectural requirements.
- Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing.
- Develop directed and random testcases, perform coverage analysis, and close functional/code coverage.
- Debug simulation failures and work closely with RTL designers to resolve issues.
- Execute regression runs, analyze results, and contribute to continuous improvements.
- Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed.
- Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains.
- Document test environments, test plans, and results for internal and external reviews.
Thanks & Regards,
Syed Quadri
Advantra Consulting Group LLC
Contact: ;
E-mail: Website:
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