What are the responsibilities and job description for the Engineer, Design Verification Engineering position at Analog Devices?
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is building out an Incubation DV Services team that’ll serve various BUs across ADI ensuring elimination of unplanned silicon iterations by boosting DV quality and embedding best practices within BUs. As part of this role, we’re seeking an early career engineer with background in electrical/computer engineering or computer science to join us as a DV engineer in our services org.
Additionally, SVV is also responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
Job Responsibilities
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is building out an Incubation DV Services team that’ll serve various BUs across ADI ensuring elimination of unplanned silicon iterations by boosting DV quality and embedding best practices within BUs. As part of this role, we’re seeking an early career engineer with background in electrical/computer engineering or computer science to join us as a DV engineer in our services org.
Additionally, SVV is also responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
Job Responsibilities
- Architect, design and develop best-in-class C/UVM based Simulation, Accelerated and Assertion based Verification IPs for latest generation complex protocols
- Create functional verification testplan from design specifications, build IP/block-level testbenches, architect coverage models, and drive to verification closure.
- Help with integration testing of IPs/blocks at subsystem and chip/system-level.
- Contribute to the development of ADI's best-in-class Testbench Generator solution to build ready to simulate IP/(sub)system-level unified testbenches for Digital, DMS and AMS.
- Support engineering DV teams to adopt in-house VIPs (including AVIP, ABVIP) and Testbench Generator, create protocol training materials, assist in debugging VIP/protocol issues
- Explore new methodologies to improve the existing solutions further.
- MS/BS in Electrical/Computer Engineering or Computer Science
- IP/Sub-system/SOC verification and/or VIP development experience is preferred
- Strong in digital design, digital verification fundamentals, SV, SVA, UVM and MDV.
- Proficient in Python/Perl (C/C is a plus)
- Strong analytical, problem-solving and debugging skills
- Highly motivated and team player
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
