What are the responsibilities and job description for the Staff Engineer, Design Verification Engineering position at Analog Devices?
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible. Learn more at www.analog.com and on LinkedIn.
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
The Role
We are looking for a highly skilled and motivated Staff Digital DV Engineer to join SVV as the lead for Digital DV methodologies. This person will soon become ADI’s go-to expert on all things SV/UVM, driving the adoption and optimization of these methods company-wide.
Key Responsibilities
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
About Us
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
The Role
We are looking for a highly skilled and motivated Staff Digital DV Engineer to join SVV as the lead for Digital DV methodologies. This person will soon become ADI’s go-to expert on all things SV/UVM, driving the adoption and optimization of these methods company-wide.
Key Responsibilities
- Lead and champion the adoption of SV/UVM-based MDV methodologies, including spec analysis, vPlan creation, and SV assertion and coverage modeling to meet stringent verification closure metrics.
- Contribute to ADI’s advanced Testbench Generator solution, helping to create unified, simulation-ready testbenches for IP and (sub)system-level verification in digital, DMS, and AMS domains.
- Develop and support in-house UVM Verification IP (VIP) and integrate third-party VIP into ADI workflows and methodologies.
- Enhance DV methodologies, leveraging AI/ML tools to optimize coverage and improve debugging productivity.
- Collaborate closely with design teams to troubleshoot and resolve DV challenges in SV, UVM, and related areas.
- Mentor and train junior engineers across the organization, helping to strengthen DV capabilities across teams.
- Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with 7-10 years of relevant experience.
- Deep expertise in SystemVerilog and UVM-based verification methodologies.
- Proficiency in developing verification environments from scratch, including vPlan/testplan development.
- Strong automation skills using languages like Perl, Python, or similar.
- Familiarity with communication protocols such as AMBA, I2C, SPI, and UART.
- Experience with industry-standard digital simulators (e.g., Cadence Xcelium, Synopsys VCS).
- Prior experience in DV of ARM/RISC-V processor-based subsystems (preferred).
- Experience in Formal Verification (preferred).
- Familiarity with Machine Learning applications in DV, especially for debug and coverage closure is a plus.
- Strong communication skills, with the ability to clearly convey technical details to both peers and product line teams.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
