Senior Principal Engineer Digital ASIC Design/Manager

• Job Title: Senior Principal Engineer Digital ASIC Design/Manager
• Location: San Diego, CA 92123, USA
• Job Type (Permanent/Contract) : Permanent
• Duration: Fulltime
• Pay Range:$300k

Description:

• Lead digital ASIC design projects from inception to production in an SOC environment.
• Hire and manage full time or contractors to support projects
• Participate in RFIC design flow by designing digital control functionality and interface to I/O and analog functions.
• Design high speed digital divider for PLL and calibration state machine.
• Perform RTL design, synthesis, P&R for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, GPIO, bus driver, state machine, registers, synchronous, asynchronous access and control function.
• Perform synthesis and P&R based on prescribed area and shape and integrate overall system.
• Perform static timing analysis & timing closure.
• Ensure integrity of physical layer design.
• Perform mixed signal verification of design.
• Perform verification with test vectors. DFT test insertion.
• Perform code coverage.
• Perform any other related duties as required or assigned.

Required Skills:
BS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1 silicon success
Proven leadership experience
Ability to improve digital design methodology to deliver high quality ICs on schedule.
Experience with mixed-signal design methodology
Ability to work with cross-functional teams and contractors across geographical boundaries.
Strong verbal and communication skills
In depth knowledge and extensive experience in digital RTL design, including Linting, Block level simulation for typical and corners, check-in with tags, placement aware synthesis with DFT insertion and RTL to gate equivalence check, pre- and post-layout timing, floor planning with clock tree synthesis and register-to-register and I/O timing, static and power analysis, vector generation and verification.
Experience with integrating ARM processor to the design. Experience with AMBA buses such as AXI/AHB/APB will be helpful.
Experience with TSMC processes.
Experience with handling of CDC and RDC is a must.
Experience with architecture definition of Mixed Signal IC.
Knowledge in Wireless Communications in 4G LTE or 5G, especially in RU will be helpful.
Experience in low power design is a must. Must know clock gating and power gating.
Knowledge of UVM verification flow.
Experience with Synopsis and Cadence tools: Virtuosos, Xcelium, Genus, Conformal, Innovus, Tempus, Joules/Voltus, JasperGold, Synopsis PrimeTime ADV, Verdi-3, Spyglass Lint, TestMax DFT and Library Compiler.
Experience with TSMC CMOS process and design kits.
Knowledge and experience with the Integration of ARM core, memory blocks, and other IP blocks a plus.
Working knowledge of other tools such as C and/or Matlab

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