What are the responsibilities and job description for the Senior Principal Engineer Digital ASIC Design / Manager position at Kyocera?

With nearly 80,000 employees globally, Kyocera is a leading manufacturer of high-tech ceramics used in various industries including aerospace, automotive, medical applications, and semiconductor processing. You will find our innovative materials in everything from smartphones to space shuttles!

Look at these PERKS !

Competitive pay, benefits, and hours
120 hours of vacation accrued per year to start (that's 3 weeks / year for regular 8-hour shifts!)
10 Paid Holidays per year
401(k)
401(k) company match
Pension
Medical insurance
Dental Insurance
Vision insurance
Life insurance
Flexible Spending Account (FSA)
Employee Assistance Program
Flexible schedules
Tuition reimbursement

We have a long-tenured staff (many with over 30 years of service!), a vital company mission, and an excellent benefits package that includes Medical, Dental, Vision, Life Insurance, Paid time off to Volunteer, paid Leave options, Tuition Reimbursement, an employer-paid Pension and a 401(k) with both Roth and a healthy company match. Many of our larger locations also feature onsite gyms, walking tracks, exercise rooms, and even employee gardens.

We strive to have a diverse workforce of people from all backgrounds, including minorities, women, and veterans, who bring their experience to support the innovation and quality that Kyocera is known for.

Senior Principal Engineer Digital ASIC Design (RFIC5395)

Exempt : Yes

Responsible for architecture of digital design. Plan and implement digital infrastructure. Plan, oversee, and execute implementation, verification, emulation, and validation of design. Identify potential high-risk areas and present possible resolutions. Drive methodology process and requirement specification documents. Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules.

Key Responsibilities :

Lead digital ASIC design projects from inception to production in an SOC environment.

Hire and manage full time or contractors to support projects.

Participate in RFIC design flow by designing digital control functionality and interface to I / O and analog functions.

Design high speed digital divider for PLL and calibration state machine.

Perform RTL design, synthesis, P&R for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, GPIO, bus driver, state machine, registers, synchronous, asynchronous access and control function.

Perform synthesis and P&R based on prescribed area and shape and integrate overall system.

Perform static timing analysis & timing closure.

Ensure integrity of physical layer design.

Perform mixed signal verification of design.

Perform verification with test vectors. DFT test insertion.

Perform code coverage.

Perform any other related duties as required or assigned.

Requirements / Qualifications :

BS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1 silicon success.

Proven leadership experience.

Ability to improve digital design methodology to deliver high quality ICs on schedule.

Experience with mixed-signal design methodology.

Ability to work with cross-functional teams and contractors across geographical boundaries.

Strong verbal and communication skills.

In depth knowledge and extensive experience in digital RTL design, including Linting, Block level simulation for typical and corners, check-in with tags, placement aware synthesis with DFT insertion and RTL to gate equivalence check, pre- and post-layout timing, floor planning with clock tree synthesis and register-to-register and I / O timing, static and power analysis, vector generation and verification.

Experience with integrating ARM processor to the design. Experience with AMBA buses such as AXI / AHB / APB will be helpful.

Experience with TSMC processes.

Experience with handling of CDC and RDC is a must.

Experience with architecture definition of Mixed Signal IC.

Knowledge in Wireless Communications in 4G LTE or 5G, especially in RU will be helpful.

Experience in low power design is a must. Must know clock gating and power gating.

Knowledge of UVM verification flow.

Experience with Synopsis and Cadence tools : Virtuosos, Xcelium, Genus, Conformal, Innovus, Tempus, Joules / Voltus, JasperGold, Synopsis PrimeTime ADV, Verdi-3, Spyglass Lint, TestMax DFT and Library Compiler.

Experience with TSMC CMOS process and design kits.

Knowledge and experience with the Integration of ARM core, memory blocks, and other IP blocks a plus.

Working knowledge of other tools such as C and / or Matlab.

Pay Range : $214,096.30 to $348,754.15 USD (Actual base pay based on factors such as relevant experience, education, market, qualifications, and skills)

How To Apply : Interested candidates must apply electronically from Kyocera International, Inc.’s site (this page).

PHYSICAL ACTIVITIES

The following physical activities described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

While performing the functions of this job, the employee is continuously required to talk or hear; regularly required to stand; frequently required to reach with hands and arms; and occasionally required to stoop, kneel, crouch, or crawl.

The employee must occasionally lift and / or move up to 25 pounds, frequently lift and / or move up to 10 pounds. Specific vision abilities required by this job include close vision.

ENVIRONMENTAL CONDITIONS

The following work environment characteristics described here are representative of those an employee encounters while performing essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

While performing the functions of this job, the employee is occasionally exposed to work near moving mechanical parts, work in high, precarious places. The noise level in the work environment is usually moderate.

ADDITIONAL INFORMATION

Tubis Technology Inc., a wholly-owned subsidiary of Kyocera International, Inc., values diversity in its workforce and is proud to be an AAP / EEO employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, you may contact Kyocera International, Inc. Human Resources team directly. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.

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Salary : $214,096 - $348,754

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