MOEMS Fabrication Engineer

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  (www.avicena.tech) 

About The Role

• Develop silicon micromachining and related processes for Micro-Opto-Electro-Mechanical Systems devices.
• Responsible for fabrication of components partially between foundry services and in-house wafer fabrication resources
• Source and manage foundry services, contractors, and vendors.
• Characterize processes and components using semiconductor metrology tools, SEM, electrical testers and optical testers.
• Work with outside laboratories to characterize processes and devices, conduct failure analyses and model optoelectronic devices
• Regularly interface with other engineers from ASIC Design, Semiconductor Packaging, Optical Packaging, Systems Engineering, and Equipment Engineering.
  
  

Requirements

• BS in Materials Science & Engineering or Mechanical Engineering.
• 10 years of related industrial experience and managing semiconductor or MEMS foundries
• Hands-on experience with micro-machining silicon, including strong knowledge of RIE, DRIE, and wet etching of silicon, as well as related lithographic masking techniques
• Strong knowledge of other MEMS-relevant materials such as sacrificial and structural layers, wet/dry release layers, SU-8, and temporary wafer bonding processes
• Strong understanding of the effects of film stresses and the management of silicon integrity
• Strong familiarity with a clean room environment and other semiconductor processing equipment, including contact aligners, steppers, ICP, CVD, PVD, ALD, plasma ashing
• Design of Experiments methodologies.
• Extremely organized, data-driven, and detail-oriented, with a strong desire to maintain thorough documentation and a baseline.
• Ability to identify, troubleshoot, and communicate significantly complex engineering problems through documentation and regular presentations to senior and executive staff members
• Familiarity with health and safety regulations in a cleanroom environment
  
  

Preferred Requirements

• MS in Engineering
• 15 years of related industrial experience
• Proficiency with layout design software tools (e.g., Tanner L-Edit)
• Scanning Electron Microscopy.
• Proficient with JMP software.
• Computer modeling and simulation (optical, thermo-mechanical) desired, but not required.
• Working level knowledge of advanced semiconductor packaging (e.g., WL-CSP, Wafer Level Packaging, 2.5D/3D packaging technology) desired, but not required.