What are the responsibilities and job description for the ASIC DESIGN FOR TEST ENGINEER position at CISCO Systems?
Job Summary
This role involves designing intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G, and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul, and ultra-long haul telecommunication networks.
Your Impact
- You will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC, and SCAN at chip and/or block level.
- You will work with seasoned DFT engineers to implement and verify DFT.
- You will interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.
Requirements
- BSEE or equivalent with 8 years of experience, or MSEE or equivalent with 6 years of experience, or PHD with 3 years of experience in ASIC DFT flows and implementation.
- Prior experience implementing scan control logic in RTLPrior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVTPrior experience with Synopsys/Mentor DFT tools
Preferred Qualifications
- Experience with scan compression and scan partitioning
- Experience with MemoryBIST, eFuse, Repair, and yield improvement techniques
- Experience with JTAG Boundary Scan Insertion AC/DC
- Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
