What are the responsibilities and job description for the Hardware Design Engineer for ASIC Test position at CISCO Systems?
Overview:
Acacia designs cutting-edge transceivers using advanced signal processing and photonic integration. This role is within the ASIC team, specifically as part of the Design for Test group. As a member of this team, you will work on setting up and implementing various test methodologies to ensure the quality and reliability of our products.
Key Responsibilities:
- Set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level
- Work with seasoned DFT engineers to implement and verify DFT
- Collaborate with RTL/PD/STA/ATE teams for successful tape out
Requirements:
- BSEE or equivalent with 8 years of experience or an MSEE or equivalent with 6 years of experience, or PHD with 3 years of experience in ASIC DFT flows and Implementation
- Prior experience implementing scan control logic in RTL
- Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVTPrior experience with Synopsys/Mentor DFT toolsPreferred Qualifications:
- Experience with scan compression and scan partitioning
- Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
- Experience with JTAG Boundary Scan Insertion AC/DC
- Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
- TCL scripting experience to automate DFT flows
Acacia designs cutting-edge transceivers using advanced signal processing and photonic integration. This role is within the ASIC team, specifically as part of the Design for Test group. As a member of this team, you will work on setting up and implementing various test methodologies to ensure the quality and reliability of our products.
Key Responsibilities:
- Set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level
- Work with seasoned DFT engineers to implement and verify DFT
- Collaborate with RTL/PD/STA/ATE teams for successful tape out
Requirements:
- BSEE or equivalent with 8 years of experience or an MSEE or equivalent with 6 years of experience, or PHD with 3 years of experience in ASIC DFT flows and Implementation
- Prior experience implementing scan control logic in RTL
- Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVTPrior experience with Synopsys/Mentor DFT toolsPreferred Qualifications:
- Experience with scan compression and scan partitioning
- Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
- Experience with JTAG Boundary Scan Insertion AC/DC
- Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
- TCL scripting experience to automate DFT flows
