ASIC Design Engineering Manager

Cornelis Networks is a technology leader delivering purpose-built, high-performance fabrics accelerating Artificial Intelligence, High Performance Computing and High Performance Data Analytics workloads in the Cloud and in the Data Center.

The company's products enable customers to solve some of the world's toughest challenges by efficiently focusing the computational power of GPUs, or AI accelerators, at scale on a single problem. Whether pursuing faster time to train on the world's frontier models, providing scale out inference, driving scientific research, or building a commercial AI application specific to an industry our high performance fabrics will improve the performance, reliability and total cost of ownership of the solution.

Cornelis Networks delivers its end-to-end interconnect solutions worldwide through an established set of server OEM and channel partners.

As an ASIC Design Engineering Manager, you will be responsible for leading an ASIC RTL Design Team and delivering block level and full-chip SoC designs of high quality. You will oversee design activities including microarchitecture, RTL development, Lint, CDC, RDC, DFT, debug support for verification and emulation, design delivery to physical design stakeholders and ECOs.

This role requires close collaboration with architecture, verification, software / firmware, emulation, and post-silicon validation teams. You will work across cross-functional teams, engaging and driving. Additionally, you will contribute to the development and execution of a strategy that aligns with the company's objectives for first pass silicon success. You will also be responsible for hiring, training, and supporting a team of ASIC engineers to ensure timely and cost-effective product development. You will also be responsible for the people management aspects to support the organizational goals.

Minimum Qualifications (post college and internships)

• 15 years' experience in ASIC / SoC design.
• 7 years' experience leading a team of direct reports.
• Expertise in RTL design, verification and debug tools such as Synopsys Spyglass, VCS, Verdi, DC and a good understanding of Fusion compiler, Primetime, Formality, Conformal.
• Expertise in revision control systems such as Git, SVN, etc.
• Proven success in first-pass ASIC development.
• Experience managing multiple projects and adjusting priorities with stakeholders.
• Strong understanding of interpreting functional specifications and creating comprehensive test plans.
• B.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience.

Preferred Qualifications

Location

For this position, Cornelis Networks fully supports remote employees who live within the United States and can travel to our corporate offices inChesterbrook, PA periodically for in-person collaboration.

Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.