What are the responsibilities and job description for the Lead ASIC Design Engineer - Synthesis, STA, Prime Time position at CyberCoders?
Job Title: Lead ASIC Design Engineer - Synthesis, STA, Prime Time
Job Location: San Jose, CA
Compensation: $160K - $240K base Depending on experience plus stock options!
Requirements: ASIC Design, Front to Back Design, Synthesis, Prime Time, STA, Lint, CDC, LEC
We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.
We are working on the world's leading edge PCIe & CXL switch and we're now looking to hire an ASIC front-to-back design sysnthesis lead.
Top Reasons to Work with Us
Responsibilities
As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements. Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis. Reponsibilities include:
Preferred
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10 - 15 years of experience:
Benefits
Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:
mike.vandenbergh@cybercoders.com
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa.
CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.
This job was first posted by CyberCoders on 07/15/2024 and applications will be accepted on an ongoing basis until the position is filled or closed.
CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. If you need special assistance or an accommodation while seeking employment, please contact a member of our Human Resources team to make arrangements.
Job Location: San Jose, CA
Compensation: $160K - $240K base Depending on experience plus stock options!
Requirements: ASIC Design, Front to Back Design, Synthesis, Prime Time, STA, Lint, CDC, LEC
We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.
We are working on the world's leading edge PCIe & CXL switch and we're now looking to hire an ASIC front-to-back design sysnthesis lead.
Top Reasons to Work with Us
- Competitive Compensation ($180K - $240K base Depending on Experience)
- Comprehensive Benefits package including stock options!
- The chance to join a small start-up tackling challenging problems with huge upside potential!
Responsibilities
As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows. You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company. You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements. Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis. Reponsibilities include:
- Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.
- Writing scripts & establishing automation for Synthesis & Prime time tools.
- Provide support for ASIC tools and flows
- Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.
- Full chip & block level timing constraints ensuring area & timing optimization
- Implement functional ECOs
- Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.
Preferred
Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10 - 15 years of experience:
- 10 - 15 years of experience in chip development & familiaritiy with ASIC CAD & EDA tools
- Knowledge with Synopsys synthesis & STA tools.
- Experience with high gate count ASICs
- Experience with ASIC methodologies such as Verilog design, Lint, Synthesis, STA & DFT.
- Strong track record of hierarchical synthesis, STA, Lint, CDC & LEC methodologies,
- Strong experience in design constraints
- Solid experience in Hierarchical Synthesis & Static timing analysis.
- Proficiency in Perl scripting for automation.
Benefits
- Medical/Dental/Vision
- PTO/Vacation Days
- Equity
Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:
mike.vandenbergh@cybercoders.com
- Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : MV1-1810598 -- in the email subject line for your application to be considered.***
For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa.
CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.
This job was first posted by CyberCoders on 07/15/2024 and applications will be accepted on an ongoing basis until the position is filled or closed.
CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. If you need special assistance or an accommodation while seeking employment, please contact a member of our Human Resources team to make arrangements.
Salary : $160,000 - $240,000
