FPGA Design and Verification Engineer

Location – San Diego, CA

Candidate must be USC/GC willing to work in W2/1099 - No C2C

Vendor referrals will not be considered

Project, main deliverables:

1. Support FPGA debug, simulation and test activities for existing platforms for defined features/escalations
2. Create updated RTL design for identified issues and block level sims utilizing UVMF
3. Support test case generation for UVMF
4. Support mono, functional & SW integration through customer delivery
5. Documentation updates/generation

Hard Skills:

Required (with demonstrated professional experience):

• Writing & Updating VHDL RTL
• Advanced in FPGA design (using VHDL) and Module / Multi-Module verification (System Verilog).
• Proficient with automated self-checking test bench verification (QuestaSim) in UVM.
• Ability to complete timing simulation/post route simulation and static timing analysis.
• Strong experience in hardware development tools and IDE for Xilinx devices (e.g. Vivado)
• Proficient in FPGA concepts, architectures and protocols (SOC, bus topology, CDC, PCIe, TSN, UART, SPI, AXI, PTP, SRIO, etc.)

Nice to have:

• Specific experience using Siemens UVMF
• Specific experience using Xilinx Zynq Ultra scale MPSOC
• Additional experience in Altera development tools

Soft Skills:

- Can read and interpret data, information, and documents.

• Creative problem solving for complex issues.
• Track record of completing assignments with attention to detail and high degree of accuracy (‘quality’)
• Ability to perform effectively in a demanding environment, within provided timelines, and with changing workloads.
• Professional communication which is clear and concise.
• Ability to establish and maintain cooperative working relationships with team members.

Best Regards,

Nisha Miriam George,

DRS IT Solutions, Inc

28175 Haggerty Road,

Novi, MI 48377

(C) 248-440-7600 EXT -3

(F) 248-859-4430