What are the responsibilities and job description for the Senior Design Verification Engineer position at Efficient Computer Service LLC?
Efficient is looking for a Digital Verification (DV) Engineer who wants to influence the next computing revolution. We are seeking an engineer with industry experience to help us in our verification efforts for our first-generation product. The DV Engineer will work on verifying Efficient’s proprietary Fabric technology by writing UVM testbenches, gathering and analyzing coverage reports, and contributing to the execution of the test plan. They will help shape our internal processes for building robust and verified designs, especially as the company scales up to higher-performance product lines.
This is a unique opportunity to get in at the ground level and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key Responsibilities
- Write modular UVM testbenches and tests to verify various design components.
- Use a constraint-random test methodology to effectively stimulate a device-under-test to increase coverage and find bugs.
- Write SystemVerilog assertions to check design invariants.
- Add cover points / groups to refine code coverage metrics.
- Collaborate with the digital design team to identify and fix bugs and coverage gaps.
- Support running gate-level simulations as part of design signoff.
- Support third-party vendor engineers when questions arise.
- Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.
- Assist in developing internal processes and frameworks to improve code quality, coverage, and correctness.
Required Qualifications & Experience
