What are the responsibilities and job description for the Design Verification Engineer position at Fairchild Imaging, Inc.?

Job Description

Fairchild Imaging, headquartered in San Jose, California is a specialty image sensor design and manufacturing company with deep experience in developing leading edge performance CMOS image sensors. Our portfolio of image sensors can be found in many high-performance imaging applications like space exploration, medical x-ray, sciences, quantum computing, machine vision, low light, and 360 situational awareness.

We are looking for a senior level digital design verification engineer who has strong proficiency in

Design Verification- executing testbench creation, functional coverage, test failures analysis, regression

Detail requirements

Solid understanding of verification methodologies, especially UVM (SystemVerilog (SV)), including :

Test planning

Test bench creation

Code and Functional coverage

Directed and random stimulus generation

Assertions

Regression triage

Defining detailed test plan and implementing Verilog simulation test cases to verify design functionality.

Build verification environment using SV / UVM methodology

Build reusable bus functional models, monitors, checkers and scoreboards

Debug product, test and resolve design issues

Integration of VIP cores Buses, Controllers, PHYs, etc with other logic within ASIC / FPGA

Because this role involves a combination of collaborative / in-person and independent work, it will take the form of a hybrid work format , with time split between working onsite and remotely.

Required Education, Experience, & Skills

Typically a BS with 10 years of experience or MS with 8 years of experience.

Desired majors Electrical Engineering, Computer Engineering, or Computer Science

Proficient in SystemVerilog (SV) language for ASIC design, and related FPGA

Knowledge of ASIC design flows is highly desirable, and FPGA is a plus

Knowledge simulation and verification methodologies (Cadence / Synopsys tool simulator, UVM)

Excellent organization and communication skills for interacting between different design groups

Proficiency in C / C and scripting languages is a plus

Fairchild Imaging provides our employees with a range in benefits offerings that includes :

9 / 80 Schedule - You get every other Friday off!

Medical, Dental and Vision coverage with multiple plan offerings

Health Savings Account with an employer contribution annually

401(k) retirement plans with Employer matching

Tuition Reimbursement

Generous Paid Time Off policy with additional Floating Holidays

The base salary range for this role is $140,000 to $200,000. Actual compensation packages are based on several factors that are unique to each candidate, including but not limited to skill set, depth of experience, and certifications.

Fairchild Imaging is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Salary : $140,000 - $200,000

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Design Verification Engineer

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