What are the responsibilities and job description for the Physical Design Engineer -Sunnyvale, CA (Hybrid) - Full time opportunity position at FSTONE Technologies?
Job Details
We have an urgent requirement "Sr. Physical Design Engineer" Full time opportunity.
Job details
Role- Physical Design Engineer
Location - Sunnyvale, CA (Hybrid)
Job description
Top-Level Physical Design:
- Chip-Level Floorplanning & Hierarchical Design Manage top-level layout planning, pin assignments, and cross-block optimizations.
- Strong scripting experience.
- Clock & Power Distribution Design robust clock trees and power delivery networks (PDN).
- Integration of IP & Sub-blocks Ensure seamless integration of IP blocks and handle complex routing challenges.
- Chip Assembly & Sign-Off Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
- DFT Integration Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.
Block-Level Physical Design:
- Floorplanning & Partitioning Define optimal floorplan with power grid, macro placements, and congestion analysis.
- Strong scripting experience.
- Placement & Optimization Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
- Clock Tree Synthesis (CTS) Design and optimize low-skew, high-performance clock networks.
- Routing & DRC Closure Ensure successful global and detailed routing, meeting design rule constraints.
- Timing Closure Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
- Power & IR Drop Analysis Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.
Regards,
Vipin Goswami
Sr. Manager -Talent Acquisition
FSTONE Technologies.
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