What are the responsibilities and job description for the Silicon Verification Engineer 5 position at HireTalent?
Job Title : Silicon Verification Engineer
Duration : months on W (High chance of extension)
Location : Mountain View, CA (Fully Remote)
Job Description
Looking for an experienced senior verification engineer with years of experience to participate in following activities :
Understand complex architecture spec and write a new test-plan / review test-plans to provide feedback on missing test-cases
UVM based TB development from scratch, including UVM sequence, scoreboard, coverage, assertions coding
Implementing DPI Calls for C reference model for checking design functionality.
UVM agent development including monitors, drivers etc.
Able to work independently / solve problems without lot of hand-holding.
Have prior experience in verifying SoCs and has knowledge of AMBA protocols.
Experienced in block level and SoC level debug.
Typical Day in the Role
Purpose of the Team : The purpose of this team is working on building IPs for silicon chips. The team is currently working on a relatively complex IP with quite a few blocks and requires support with IP verification.
Key projects : This role will contribute to IP verification and writing test cases for high level testing support using SystemVerilog and UVM in a C based environment.
Typical task breakdown and operating rhythm : The role will consist of mostly heads down work, with only a few hours of meetings per week. This role will spend most of their time working in the verification environment site, with most of that time spent on debugging. The role will be largely independent, while the team is always encouraged to ask for help or insight when needed the role will have minimal hand-holding once ramped up.
Compelling Story & Candidate Value Proposition
What makes this role interesting? - This role provides the opportunity to work on very complex IP level verification that will be a great challenge and will use all kinds of verification aspects.
Unique Selling Points : The role will have a high impact on important IP that will be great on a resume.
Candidate Requirements
Years of Experience Required : overall years of experience in the field.
Degrees or certifications required : No degree is required to be eligible for this role.
Disqualifiers : Candidates that do not have most of their experience in verification / have mostly validation experience or do not have recent experience in verification will not be eligible for the role. The team is looking for strong individual contributors to do hands-on development and debug, and is not looking for a people manager or lead to fill these roles.
Best vs. Average : The ideal resume would contain significant experience with IP verification as well as systemverilog assertions coding and knowledge of C. Supplemental experience with FGPA based platform debugging tests is helpful on top of having the necessary SoC experience.
Performance Indicators : Performance will be assessed based on meeting deliverables and deadlines, with their work tracked in Azure DevOps.
Top Hard Skills Required Years of Experience
Minimum years experience with verification for SoCs including a knowledge of AXI / AMBA protocols.
Minimum years experience with writing test-plans for complex IP architecture – not doing test plans anymore, dev and debug for SoC level test, develop and debug test for SoC
Minimum years experience with UVM based TB development from scratch, including UVM sequence, scoreboard, coverage, assertions coding
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