SystemVerilog/UVM/SoC Design Verification Engineer

Role: SystemVerilog/UVM/SOC Design Verification Engineer

Location: Redmond, WA (Hybrid, Remote option allowed)

Job Type: Contract

Interview: Phone/Skype

Join our team to verify and validate cutting-edge SOC designs!

Key Responsibilities:

• Implement and define SoC verification plans

• Develop functional tests and verification environments

• Debug and resolve design failures

• Collaborate with cross-functional teams to ensure design quality

• Drive continuous verification improvements

Experience & Skills:

• 8-10 years in SystemVerilog/UVM methodology

• Bachelor's in Computer Science, Computer Engineering, or related field

• Experience with EDA tools and scripting (Python, TCL, Perl, Shell)

• Track record of 'first-pass success' in ASIC development

Preferred:

• Experience verifying GPU/CPU designs

• Development of UVM-based verification environments

• Knowledge of high-speed interfaces (PCIe, DDR, Ethernet)

• Familiarity with revision control systems (Mercurial, Git, SVN)

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