Sr. Design Verification Engineer

Overview

We are seeking a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. In this role, you will work on complex SoC designs and collaborate with various teams to ensure the successful development and validation of our products.

Sunnyvale, CA or Austin, TX

2 year Project

Responsibilities

• Collaborate with cross-functional teams to ensure the effective verification of complex SoC designs.
• UVM Expertise
• Develop and maintain scripts using languages like Perl, Python, Unix shells, and Makefiles to automate testing and verification processes.
• Gain an in-depth understanding of high-speed interfaces, including PCIe, USB, NOC, NVMe, Ethernet, LPDDR5, and HBM2, to ensure seamless integration into complex SoC designs.
• Collaborate with lab managers to set up and manage the necessary infrastructure for emulation and verification activities.
• Contribute to the development of comprehensive verification plans, testbenches, and methodologies.
• Identify and propose improvements to streamline the emulation and verification process.
  
  
  

Requirements

• Bachelor's or higher degree in Electrical Engineering, Computer Science, or a related field. ✔ 8 years of SystemVerilog/UVM experience (IP, sub-system, or SoC level verification)
  
  
  

✔ Strong scripting skills (Python, TCL, Perl, Shell) for automation and tool development

✔ EDA tool expertise (VCS, Xcelium, Questa, Verdi, Spyglass, etc.)

✔ Experience in debugging, root-cause analysis, and driving verification closure

✔ Familiarity with CPU/GPU verification, AI/ML, Networking, or micro-architectural performance verification is a plus

✔ High-speed interface verification (PCIe, DDR, HBM, Ethernet, RoCE) preferred