What are the responsibilities and job description for the Design Verification Engineer position at Quest Global?
Hello!!!
Looking for an exciting role with Quest Global for Design Verification :
Skill : DV, UVM, System Verilog,
Location - Austin or San Jose location.
Notice Period - Immediate - 15days
Job Description
- Very fast paced environment.
- Excellent SV / UVM knowledge.
- Good to have : LPDDR / DDR protocol knowledge.
If interested, please share your updated resume at sanghamitra.mohanty@quest-global.com
