What are the responsibilities and job description for the Silicon Verification Engineer position at SAR TECH LLC?
Job Details
Contract Length: Initial 6-month contract (potential to go 18-months)
Location:100% onsite in either Sunnyvale, CA, San Francisco, CA or Austin TX
Industry: Social Media
Work Authorization: Prefers G.C or U.S Citizen.
Minimum Requirements
- Ideal range is 10-15 years: However, they are open to candidates with 7-20 years of experience
- Semiconductor background is a must
- Experience in the semiconductor industry is essential.
- The focus is on System Verilog and UVM expertise
- Hands-on experience in Verilog, System Verilog, C/C based verification, and UVM methodology
- Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
- Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
Preferred Qualifications
- Experience in the development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
- Experience with revision control systems like Mercurial(Hg), Git or SVN
- Experience with verification of ARM/RISC-V based sub-systems or SoCs
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Silicon Verification Engineer 5
Randstad Digital -
Mountain View, CA
Pre - Silicon Verification Engineer
Advanced Micro Devices, Inc -
San Jose, CA
Pre-silicon Verification Engineer
Intel Corporation -
Santa Clara, CA
