What are the responsibilities and job description for the FPGA / ASIC Design Verification position at SEDAA?

Job Description

Job Title - FPGA / ASIC Design Verification

Location- San Jose, CA (Onsite)

Work involves more interactions with team, expected to work onsite most of the time

L ooking for candidate with mid-level (7-8 years) verification experience, with total experience not more than 10 years.

Responsibilities :

Own verification of entire FPGA design used in high end router products
Understand the design specification and interact with design engineers to identify verification scenarios.
Create test plan, constrained-random verification environment, testcases, regressions and coverage reports.
Identify and write all types of coverage measures for stimulus and corner-cases.

Qualifications :

Strong academic background in Electrical Engineering (Bachelor's required, master’s preferred)

7-8 years of pure verification experience in ASIC / FPGAs

Proficient in SystemVerilog with clear OOP concepts

Experience developing object-oriented testbench infrastructure, BFMs, testcases in UVM

Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO etc.

Understanding of verifying IP integrations, strategies, corner cases etc.

Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures

Experience with scripting language like Perl, Python is a plus

Proficiency with industry-standard tools, revision control systems, and regression systems.

Expectations :

Professional attitude, good team member with the ability to prioritize tasks and work independently

Agility to work on multiple tasks / projects in parallel, adaptability and flexibility to switch tasks based on priorities

Good communication skills

Work involves more interactions with team, expected to work onsite most of the time

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