What are the responsibilities and job description for the FPGA/ASIC Verification Designer position at SEDAA?
Job Title -FPGA/ASIC Verification Designer
Location- San Jose, CA
Other preferences:
- Cisco experience preferred
- Worked with high speed power 10g plus.
- Experience PCI Express Design
- should have good communication skills
Job Description:
Candidate will be responsible for taking networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional team to address development requirements, participate in validation of the system, and release to manufacturing
Here is a list of requirements
- FPGA development expertise from specification to production,
- Verilog/System Verilog RTL coding
- Knowledge of industry leading FPGA devices and tools,
- Familiarity with UVM and/or VMM DV methodology,
- Experience with high speed design debug,
- Experience with advanced microprocessor based design
- Proficiency with lab equipment such as scope and analyzer
- Good communication and cross functional team skills
Education/Experience:
- Bachelor's Degree in Computer Engineering or related field
- Prior experience required
- Previous lab experience a must
