PCIe Protocol Engineer (Tech Staff Engineer)

The Candidate will be an expert with 32Gbps SERDES (Serializer / Deserializer) based protocols, and must possess recent work experience with PCIe Rev.3, 4 and 5 protocol.

Minimum Qualifications :

• BSEE / BSCS with 10 years of experience.
• Knowledge of FPGA architectures is a must.
• Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios.
• Strong technical background in FPGA prototype emulation, and debug.
• Strong technical background in silicon validation, failure analysis and debug.
• Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal).
• Design with RTL coding in Verilog and VHDL is a must.
• Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools.
• Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
• Familiarity with the bring up and on-board debug of 32Gbps SERDES.
• Hands-on systems level design and debug experience with following high-speed serial communications protocols (must : PHY, PCS and Data link layer of the OSI protocol stack; desirable : transaction and upper layers of the OSI protocol) :
• PCIe Gen3 / 4 / 5
• Experience with the PCI-SIG Compliance Tests :
• Protocol Testing
• PCI-CV Testing
• PHY Testing
• Experience with the PCIe Lab Equipment :
• PCIe Analyzer
• PCIe Exerciser
• Strong commitment to quality and customer satisfaction.
• Excellent verbal and written communication skills in English.
• Able to travel 0-2 times annually if required.

Preferred Qualifications :

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