What are the responsibilities and job description for the Application Specific Integrated Circuit Verification Engineer position at Tara Technical Solutions (TTS)?
High Speed ASIC AI Chip Team:
We are seeking a highly skilled engineer to join our team in San Jose, working on-site daily.
The ideal candidate will conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon.
They will also develop system-level tests using Tcl, ITcl, Python, C/C to verify networking switch chips and systems, and synthesize Verilog RTL and build models for emulation platforms such as Zebu or Palladium.
In addition, the successful candidate will possess debugging expertise, performing chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges.
A key aspect of this role is automation and methodology development. The engineer will create reusable synthesizable design blocks, libraries, and verification components to streamline emulation, and develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value.
Silicon bring-up planning, organization, and execution are also crucial responsibilities of this position.
Key qualifications include experience with C/C DPI Transactors, SystemVerilog assertions, and coverage metrics, as well as proven ability to design and develop synthesizable models for emulation, hands-on experience with IXIA/Spirent traffic generators for networking validation, strong understanding of networking protocols and RFC test suites, and familiarity with communication/interface protocols like PCIe, SPI, and JTAG.
