What are the responsibilities and job description for the Sr. DFT Engineer (SERDES/HBM/DDR) position at Theery?
Job Description:
We are looking for a highly skilled HBM and SerDes DFT Verification Engineer to join a dynamic engineering team. In this role, you will play a critical part in ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies. You will work closely with cross-functional teams to develop, implement, and validate DFT methodologies, ensuring that products meet the highest quality standards.
Responsibilities:
- Implement and verify DFT methodologies specifically for HBM, DDR, and SerDes designs.
- Collaborate with design and architecture teams to identify and define key testability requirements.
- Utilize advanced simulation tools and methodologies to verify DFT implementations.
- Analyze DFT-related data and provide insights for continuous design improvements.
- Document verification processes, results, and best practices to enhance team knowledge and efficiency.
- Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.
- Work closely with STA and DI Engineers to achieve design closure for test.
- Generate, verify, and debug test vectors before tape release.
- Validate and debug test vectors on ATE during the silicon bring-up phase.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design teams, and test engineering/manufacturing teams globally.
- Collaborate with I/P DFT engineers and other stakeholders.
- Debug customer-returned parts on the ATE.
- Innovate new DFT solutions to address testability challenges in cutting-edge IPs (e.g., 3nm and beyond).
- Automate DFT and test vector generation flows.
Skills/Experience:
- Strong background in DFT (such as Analog DFT, MBIST, IEEE1687, and others).
- Proven experience in DFT verification, particularly with HBM, DDR, PCIe, and other SerDes IPs.
- Understanding of DFT methodologies, including scan, BIST, and ATPG.
- Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL, Ruby).
- Excellent analytical and problem-solving skills.
- Strong communication and teamwork abilities.
- Ability to work in a multi-disciplinary, cross-department environment.
- Solid knowledge in analog and digital circuit design, and device physics fundamentals.
- Excellent problem-solving, debugging, root cause analysis, and communication skills.
- Experience working on ATE is a plus.
- Familiarity with BIST logic for array and link testing is a plus.
- Knowledge of AHB/APB/AXI buses is a plus.
Education & Experience:
- Bachelor’s degree in Electrical/Electronic/Computer Engineering with 8 years of relevant industry experience, or a Master’s degree in Electrical/Electronic/Computer Engineering with 6 years of relevant industry experience.
Please apply here with your updated resume or send directly to Kevin@Theery.com
Salary : $125,000 - $188,000