What are the responsibilities and job description for the Senior UVM Verification Engineer position at Triple Crown?
Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.
CONTRACT Position: 2-18 Months
Location: Onsite in Sunnyvale, CA (partial remote flexibiity - 50% onsite weekly)
*Must be U.S. Citizen or U.S. Person*
As a Senior UVM (Universal Verification Methodology) Verification Engineer you will be responsible for designing, implementing, and executing verification environments for complex ASIC or FPGA designs using UVM methodology. This role requires strong experience in verification techniques, UVM framework, and the ability to work on both block-level and system-level verification.
- Years of Experience Required: 10 overall years of experience in this field.
- Degrees or certifications required: Bachelor's in computer science, Electrical/Electronics 7 years verification experience using UVM/System Verilog Methodology OR Masters in computer science, Electrical/Electronics 5 years verification experience using UVM/System Verilog Methodology is required to be eligible for this role.
- Disqualifiers: Candidates with missing requirements & running tests but not taking tests from start to finish will not be eligible for the role.
- Best vs. Average: The ideal resume would contain UVM and System Verilog based verification experience.
Skills:
- UVM
- System Verilog
- Scripting
Benefits:
- Paid weekly!
- Health, Dental and Vision Insurance
- 401k
