What are the responsibilities and job description for the Senior ASIC Engineer, Static Timing Analysis position at US Tech Solutions?
DURATION: 6 months contract
JOB DESCRIPTION:
- Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets.
- Summarize the regression results periodically to track the progress.
- Able to debug the basic issues like SDC loading errors, check_timing (no_clock, unconstrained, no_clock, QoR violations).
REQUIREMENTS:
- Attention to the detail.
- Very good communication skills (both written and verbal).
- Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions).
SKILLS:
- Worked with EDA tools that enable RTL quality checks
- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Ability to multitask, ramp up quickly on new flows/tools/ideas
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable
EXPERIENCE:
- Minimum of 6-8 years' experience.
EDUCATION:
- Bachelor's degree required
About US Tech Solutions:
US Tech Solutions (www.ustechsolutionsinc.com) is global firm providing a wide-range of talent on-demand and total workforce solutions. We are an Equal Opportunity Employer and Prohibit Discrimination and Harassment of Any Kind.
U.S. Tech Solutions, Inc. is an Affirmative Action, Equal Opportunity Employer. Our employment decisions are made without regard to race, color, religion, gender, national origin, age, disability, marital status, veteran or military status, or any other legally protected status.
Recruiter Details:
Name: Megha Arora
Email: meghaa@ustechsolutionsinc.com
Internal Id: 25-30093
Salary : $75 - $85
