Contract Hardware Engineer Mid.

Duties: Location: Remote within USA Experince: 7 Years What are the top non-negotiable skill sets required for this role?Power and performance modeling or DV (C, system C, system Verilog, or matlab)Strong DV background (test plan development, test writing, UVM)Experience with low power verification (UPF)Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flowsDuties:Responsible for low power verification including both dynamic and static verificationWrite and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional, code, and power coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leadsSkillsMust Have:7 years of proven experience as a DV engineero Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verificationHands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsExperience with UPF based simulation flow2 Years of experience with C/C Wish List/ Nice to Have:Power and performance FPGA validationHifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.Experience with Power Aware GLS flowTcl and Python (or similar) scripting languageASIC design experienceExperience in formal property verification of complex compute blocks like DSP, CPU or HW acceleratorsExperience with complex SoCsKnowledge of coverage merging across simulation and formalMSEE/CS or equivalent experience

Skills: Location: Remote within USA Experince: 7 Years What are the top non-negotiable skill sets required for this role?Power and performance modeling or DV (C, system C, system Verilog, or matlab)Strong DV background (test plan development, test writing, UVM)Experience with low power verification (UPF)Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flowsDuties:Responsible for low power verification including both dynamic and static verificationWrite and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional, code, and power coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leadsSkillsMust Have:7 years of proven experience as a DV engineero Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verificationHands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsExperience with UPF based simulation flow2 Years of experience with C/C Wish List/ Nice to Have:Power and performance FPGA validationHifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.Experience with Power Aware GLS flowTcl and Python (or similar) scripting languageASIC design experienceExperience in formal property verification of complex compute blocks like DSP, CPU or HW acceleratorsExperience with complex SoCsKnowledge of coverage merging across simulation and formalMSEE/CS or equivalent experience

Education: EducationMust Have: Bachelor degree in Electrical/Computer Engineering or Computer ScienceMaster's Degree preferred but not required

Required Skills: DSP,C/C ,MSEE,ASIC,FPGA,
Additional Skills: ARTICULATE,TEST PLANS,TCL,DEBUG,PYTHON,SCRIPTING,PERFORMANCE MODELING,TEST PLAN,FIELD PROGRAMMABLE GATE ARRAY,VERILOG,NATURAL LANGUAGE PROCESSING,CADENCE,SOCS,SYNOPSYS,MATLAB,

Minimum Degree Required: Bachelor's Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak, Read, Write )
Department: Regional Recruiting Services : 7134
Job Category: IT